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Analog-to-Digital Converter (ADC)
The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency.
UCF Location Constraints
Figure 10-5 provides the User Constraint File (UCF) constraints for the amplifier interface,
including the I/O pin assignment and I/O standard used.
NET
NET
NET
NET
"SPI_MOSI"
"AMP_CS"
"SPI_SCK"
"AMP_SHDN"
LOC
LOC
LOC
LOC
=
=
=
=
"AB14"|
"W6" |
"AA20"|
"W15" |
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
LVTTL
LVTTL
LVTTL
LVTTL
|
|
|
|
SLEW
SLEW
SLEW
SLEW
=
=
=
=
SLOW
SLOW
SLOW
SLOW
|
|
|
|
DRIVE
DRIVE
DRIVE
DRIVE
=
=
=
=
8 ;
4 ;
12 ;
4 ;
NET
"AMP_DOUT"
LOC
=
"T7" |
IOSTANDARD
=
LVTTL
;
Figure 10-5:
UCF Location Constraints for the Pre-amplifier Interface (AMP)
Analog-to-Digital Converter (ADC)
The LTC1407A-1 provides two ADCs. Both analog inputs are sampled simultaneously
when the AD_CONV signal is applied.
Interface
Table 10-3 lists the interface signals between the FPGA and the ADC. The SPI_SCK signal
is shared with other devices on the SPI bus. The active-High AD_CONV signal is the
active-Low slave select input to the DAC. The DAC_CLR signal is the active-Low,
asynchronous reset input to the DAC.
Table 10-3:
ADC Interface Signals
Signal
FPGA Pin
Direction
Description
SPI_SCK
AD_CONV
ADC_OUT
AA20
Y6
D16
FPGA ADC Clock
FPGA ADC Active-High, initiates conversion process.
FPGA ADC Serial data. Presents the digital representation of the
sample analog values as two 14-bit two’s
complement binary values.
SPI Control Interface
Figure 10-6 provides an example SPI bus transaction to the ADC.
When the AD_CONV signal goes High, the ADC simultaneously samples both analog
channels. The results of this conversion are not presented until the next time AD_CONV is
asserted, a latency of one sample. The maximum sample rate is approximately 1.5 MHz.
The ADC presents the digital representation of the sampled analog values as a 14-bit, two’s
complement binary value.
Spartan-3A FPGA Starter Kit Board User Guide
UG330 (v1.3) June 21, 2007
www.xilinx.com
81
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